fix generation of virtual ports
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1 changed files with 2 additions and 2 deletions
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@ -78,7 +78,7 @@ impl VirtualPort{
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let masked_val = val & 0x0F;
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assert_eq!(masked_val, val);
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Self((self.0 & 0xF0) | masked_val)
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Self((self.0 & 0x0F) | (masked_val << 4))
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}
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#[inline]
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@ -86,7 +86,7 @@ impl VirtualPort{
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let masked_val = val & 0x0F;
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assert_eq!(masked_val, val);
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Self((self.0 & 0x0F) | (masked_val << 4))
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Self((self.0 & 0xF0) | masked_val)
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}
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#[inline]
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