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fix generation of virtual ports

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DJMrTV 2025-01-19 19:09:42 +01:00
commit ad86a74efb
1 changed files with 2 additions and 2 deletions
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4
src/prudp/packet.rs
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@ -78,7 +78,7 @@ impl VirtualPort{
let masked_val = val & 0x0F; let masked_val = val & 0x0F;
assert_eq!(masked_val, val); assert_eq!(masked_val, val);
Self((self.0 & 0xF0) | masked_val) Self((self.0 & 0x0F) | (masked_val << 4))
} }
#[inline] #[inline]
@ -86,7 +86,7 @@ impl VirtualPort{
let masked_val = val & 0x0F; let masked_val = val & 0x0F;
assert_eq!(masked_val, val); assert_eq!(masked_val, val);
Self((self.0 & 0x0F) | (masked_val << 4)) Self((self.0 & 0xF0) | masked_val)
} }
#[inline] #[inline]